A flash memory is a non-volatile electrically erasable data storage device that evolved from electrically erasable programmable read-only memory (EEPROM). The two main types of flash memory are named after the logic gates that their storage cells resemble: NAND and NOR. NAND flash memory is commonly used in solid-state drives, which are supplanting magnetic disk drives in many applications. A NAND flash memory is commonly organized as multiple blocks, with each block organized as multiple pages. Each page comprises multiple cells. Each cell is capable of storing an electric charge. Some cells are used for storing data bits, while other cells are used for storing error-correcting code bits. A cell configured to store a single bit is known as a single-level cell (SLC). A cell configured to store two bits is known as a multi-level cell (MLC). In an MLC cell, one bit is commonly referred to as the least-significant bit (LSB), and the other as the most-significant bit (MSB). A cell configured to store three bits is known as a triple-level cell (TLC). Writing data to a flash memory is commonly referred to as “programming” the flash memory, due to the similarity to programming an EEPROM.
The electric charge stored in a cell can be detected in the form of a cell voltage. To read an SLC flash memory cell, the flash memory controller provides one or more reference voltages (also referred to as read voltages) to the flash memory device. Detection circuitry in the flash memory device will interpret the bit as a “0” if the cell voltage is greater than a reference voltage Vref and will interpret the bit as a “1” if the cell voltage is less than the reference voltage Vref. Thus, an SLC flash memory requires a single reference voltage Vref. In contrast, an MLC flash memory requires three such reference voltages, and a TLC flash memory requires seven such reference voltages. Thus, reading data from an MLC or TLC flash memory device requires that the controller provide multiple reference voltages having optimal values that allow the memory device to correctly detect the stored data values.
Determining or detecting stored data values using controller-provided reference voltages is hampered by undesirable physical non-uniformity across cells of a device that are inevitably introduced by the fabrication process, as such non-uniformity results in the reference voltages of different cells that store the same bit value being significantly different from each other. The detection is further hampered by target or optimal reference voltages changing over time due to adverse effects of changes in temperature, interference from programming neighboring cells, and numerous erase-program cycles. Errors in detecting stored data values are reflected in the performance measurement known as bit error rate (BER). The use of error-correcting codes (ECCs) can improve BER to some extent, but the effectiveness of ECCs diminishes as improved fabrication processes result in smaller cell features.
As illustrated in FIG. 1, an MLC flash memory has four cell voltage distributions 102, 104, 106 and 108 with four respective mean target cell voltages Vtarget0 112, Vtarget1 114, Vtarget2 116 and Vtarget3 118. Such cell voltage distributions commonly overlap each other slightly, but such overlap is not shown in FIG. 1 for purposes of clarity. During a read operation, to attempt to characterize or detect the two bits of cell data (i.e., the LSB and MSB) a flash memory device (not shown) uses three reference voltages it receives from a flash memory controller (not shown): Vref0 122, Vref1 124 and Vref2 126. More specifically, the flash memory device compares the cell voltage with Vref1 124 to attempt to detect the LSB. If the flash memory device determines that the cell voltage is less than Vref1 124, i.e., within a window 128, then the flash memory device characterizes the LSB as a “1”. If the flash memory device determines that the cell voltage is greater than Vref1 124, i.e., within a window 130, then the flash memory device characterizes the LSB as a “0”. The flash memory device also compares the cell voltage with Vref0 122 and Vref2 126 to attempt to detect the MSB. If the flash memory device determines that the cell voltage is between Vref0 122 and Vref2 126, i.e., within a window 132, then the flash memory device characterizes the MSB as a “0”. If the flash memory device determines that the cell voltage is either less than Vref0 122 or greater than Vref2 126, i.e., within a window 134, then the flash memory device characterizes the MSB as a “1”.
The most commonly employed ECCs are hard-decoded codes, such as BCH codes. To improve BER beyond what is commonly achievable with hard-decoded ECCs, flash memory controllers may employ soft-decoded ECCs, such as low density parity check (LDPC) ECCs. Soft decoding is more powerful in correcting errors than hard decoding, but soft input information must be provided to the ECC decoding logic. The ECC decoder soft input information is commonly provided in the form of log likelihood ratio (LLR) information. Since a flash memory device conventionally only provides hard decision outputs, i.e., it characterizes each data bit that it reads as either a “1” bit or a “0” bit in the manner described above, employing soft decoding requires that the flash memory controller generate ECC decoder soft input information.
One method that has been employed for generating ECC decoder soft input information (e.g., LLRs) in an MLC flash memory controller involves computing a function of the reference voltages used to read the memory device and the means and variances of the four cell voltage distributions 102, 104, 106 and 108. A faster method that has been employed for generating ECC decoder soft input information in a flash memory controller has been to map a “1” bit (hard decision) to a first fixed or predetermined value and map a “0” bit (hard decision) to a second fixed or predetermined value. For example, a “1” bit may be mapped to a decimal value of “6”, and a “0” bit may be mapped to a decimal value of “−6”. Thus, such a flash memory controller's ECC decoding logic would use decimal “6” as soft input information in response to the flash memory device reading a “1” bit and would use decimal “−6” as soft input information in response to the flash memory device reading a “0” bit. The decimal value pair of “+6” and “−6” are still hard decision values in a strict mathematical sense, but it is understood that hard decision values are a special case of soft decision values.
Despite the benefits of employing soft-decoded ECCs, a page read sometimes fails. That is, the BER is so great that ECC decoding is unable to correct all erroneous bits. A common method for responding to such a page read failure is known as a “retry” or “read retry.” In a read retry, the flash memory controller may adjust the reference voltage that was used to read the page and then try to read the page again using the adjusted reference voltage.
To improve BER, it would be desirable to provide an improved method and system for generating LLR information from flash memory device hard decision outputs.